IEEE APCCAS 2018 solicits proposals for special sessions within the technical scope of the conference. Special sessions supplement the regular program of the conference and provide a sample of the state-of-the-art research in both academia and industry in special, novel, challenging, and emerging topics.

Special-session proposals should be submitted by the prospective organizer(s) who will commit to promoting and handling the review process of their special session as Chairs or Co-Chairs of the event. Proposals should include the following information:

• Title;
• Name(s) of organizer(s);
• Email of main contact person;
• Brief bio(s) of organizer(s);
• Brief description;
• Related topics;
• Potential participants;
• A draft of the CFP (please download and use the template at the link below);
• Description of publicity and promotion plan;
• Brief report on past editions of the special session, if any, including the number of submitted and accepted papers, the number of attendees, etc.

Papers submitted to special sessions will have to be evaluated and peer-reviewed along the very same criteria of the regular sessions.

Important Dates

• Submission of Special Sessions Proposals: July 25, 2018 July 31, 2018
• Submission of Papers of special sessions: July 30, 2018 July 31, 2018
  Notification of Review Result of Papers from Special Sessions: August 30, 2018

Please provide all the information requested above when preparing your special-session proposal before submitting it in PDF format by E-mail to APCCAS 2018.

Special Session - Call for Paper

• Special Session 1: Emerging threats in the IoT era: chip reliability and security
  Chair: Terrence Mak, University of Southampton, UK
  Co-chair: Xiaohang Wang, South China University of Technology, China
  
  
  • Topic：
    1. hardware Trojan design and countermeasure
    2. analysis of side and covert channel for both 2D and 3D chips
    3. timing, reliability, variability, power-related attacks for IoT chips
    4. secure and trustworthy IoT chip architecture
    5. ultra low power and reliable IoT chip design
    
    
    
• Special Session 2: Reconfigurable Architecture for Future Intelligent Systems (Read More)
  Chair: Shunqing Zhang, Shanghai Institution for Advanced Communication and Data Science, Shanghai University, China
  Co-chair: Yadong (Bill) Yuan, Programmable Solutions Group, Intel Corporation, China
  
  

  • Topic：
    1. FPGA based reconfigurable AI accelerator
    2. Systematic design for intelligent applications using FPGA based solution
    3. FPGA-based low-power objective detection and analysis for automatic driving and computer vision
    4. Reconfigurable architecture with FPGA verfication
    5. FPGA based heterogeneous computing platform
    
    
    

  Special Session 3: Smart and Secure Integrated Systems for Autonomous Vehicles (Read More)
  Chair: Anupam Chattopadhyay, Nanyang Technological University, Singapore
  Co-chair: Zheng Wang, Shenzhen Institutes of Advanced Technology, China

  • Topic：
    1. Blockchain-based Protocol for AV Data Aggregation
    2. Multi-Scale Multi-Domain Co-Simulation for Rapid Advanced Driver Assistance Systems (ADAS) Prototyping
    3. Security Primitives and Attacks for Autonomous Vehicles
    4. Low-cost vector map assisted navigation strategy for autonomous vehicle
    5. Accelerator design for convolutional neural network with vertical address reflection
    6. A CGRA based AI inference engine supporting supervised and reinforcement learning

  
  
  Special Session 4: Hardware Security and Hardware Implementation of Post-Quantum Cryptography (Read More)
  Chair: Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, Nanjing, China
  Co-chair: Chongyan Gu, Queen’s University Belfast, UK
  
  

  • This session focuses on the security challenges raised due to the development of IoT and quantum computers. Original researches on hardware security and hardware implementation of post-quantum cryptography are welcomed.

  
  
  

  Special Session 5: Artificial Intelligent (AI) System and Advanced Processing (AP) Core Technology (Read More)
  Chair: Lan-Da Van, National Chiao Tung University, Taiwan
  Co-chair: Hongbin Sun, Xi'an Jiaotong University, China
  

  • Due to the rapid advanced of general-purpose GPU (GPGPU) and multicore CPU and Application-Specific Integrated Circuits (ASIC), the artificial intelligence (AI) system technology and advanced processing (AP) core technology could be evolved such that emerging applications can be realized. In this special session, AI and AP research works will be addressed. Fusing AI system technology and AP core technology will be the future goal.

  
  
  

  Special Session 6: Future Circuits and Systems based on Emerging Memory Technologies (Read More)
  Chair: Weisheng Zhao, Beihang University, China
  Co-chair: Wang Kang, Beihang University, China
  

  • With the end of Moore's law in sight, the semiconductor industry has been in a 'the King is dying' phase owing to the "power wall" issue. Meanwhile, the "memory wall" in typical von-Neumann computing architecture accelerates the power wall issue due to the separation of the processor and memory (or refer to "von-Neumann bottleneck"). Many emerging memory technologies, especially nonvolatile memory technologies, such as MRAM and RRAM, etc., are looking into fill the ensuing power vacuum and bringing new innovation for future circuits and systems. This session aims to bring together the worldwide leading experts related to this topic to share recent results on "Future Circuits and Systems based on Emerging Memory Technologies". We believe attendees from different fields will benefit from this special session.

  
  
  

  Special Session 7: Design and Implementation for Advanced Baseband Signal Processing (Read More)
  Chair: Chuan Zhang, National Mobile Communications Research Laboratory, Southeast University, China
  Co-chair: Shan Cao, Shanghai Institution for Advanced Communication and Data Science, Shanghai University, China
  

  • Topics:
    1. Advanced channel coding algorithms and implementations for 5G;
    2. Massive MIMO, particularly signal processing and hardware challenges;
    3. Algorithms and hardware implementations related to non-orthogonal multiple-access schemes;
    4. Algorithms and hardware implementations for 5G modulation: non-orthogonal modulation and demodulation, FMBC modulation and others;
    5. Algorithms and hardware implementations related to AI-based baseband processing;
    6. Hardware-software co-design for baseband communications;