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Keynote Speakers
Keynote Speakers

 

Ming Liu,
Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), China

Biography: Ming Liu received the B.S. and M.S. degrees in semiconductor physics and device from Hefei Polytechnic University, Hefei, China, in 1985 and 1988, respectively, and the Ph.D. degree in microelectronics from Beijing University of Aeronautics and Astronauts, China, in 1998. From 1998 to 1999, she was a Postdoctoral Scholar in the Chinese Academy of Sciences (CAS). She joined the Institute of Microelectronics, CAS, in 2000. She is currently the Director of the Key Laboratory of Nanofabrication and Novel Devices Integration Technology and the Key Laboratory of Microelectronics Devices and Integrated Technology. She was selected as an Academician of Chinese Academy of Sciences and IEEE Fellow in 2015 and 2018 separately. Her research interests are semiconductor materials, integrated circuit processing, nanofabrication, nano-electronics, molecular electronics, and non-volatile memory.

Speech Title: Developing Status and Trend for Nonvolatile Memory
Abstract:
The common memory technologies used in the traditional memory hierarchy, are increasingly constrained by fundamental technology limits. The increasing leakage power for SRAM and refresh dynamic power for DRAM has posed challenges to circuit and architecture designers. Emerging memory technologies such as spin transfer torque RAM (STT-RAM), phase-change RAM (PCRAM), and resistive RAM (RRAM) are being explored as potential alternatives to existing memories in future computing systems. Especially, due to the excellent compatibility with CMOS process and ease of 3D integration, RRAM provides a promising potential for embedded and standalone application. In this talk, current status of RRAM technology will be discussed, including switching mechanism, array architecture, 3D integration, target applications, challenges and future trends. A new era of convolutional computer architectures could be expected after the mature of emerging new NVM technologies.

 

Yong Lian,
Fellow of Academy of Engineering Singapore, Fellow of IEEE
President, IEEE Circuits and Systems Society
Member, IEEE Fellow Committee

Bography: Dr. Yong Lian received the B.Sc degree from the College of Economics & Management of Shanghai Jiao Tong University in 1984 and the Ph.D degree from the Department of Electrical Engineering of National University of Singapore (NUS) in 1994. He worked in industry for more than 9 years before joining NUS in 1996. He was appointed as the first Provost’s Chair Professor in the Department of Electrical and Computer Engineering of NUS in 2011. His research interests include low power techniques, continuous-time signal processing, biomedical circuits and systems, and computationally efficient signal processing algorithms. His research has been recognized with more than 20 awards including the 1996 IEEE Circuits and Systems Society's Guillemin-Cauer Award, the 2008 Multimedia Communications Best Paper Award from the IEEE Communications Society, 2011 IES Prestigious Engineering Achievement Award, 2012 Faculty Research Award, 2013 Outstanding Contribution Award from Hua Yuan Association and Tan Kah Kee International Society, 2014 Chen-Ning Yang Award in Science and Technology for New Immigrant, and the 2015 Design Contest Award in 20th International Symposium on Low Power Electronics and Design. He is also the recipient of the National University of Singapore Annual Teaching Excellence Awards in 2009 and 2010, respectively.

Dr. Lian is the President of the IEEE Circuits and Systems (CAS) Society, a member of IEEE Fellow Committee, a member of IEEE Biomedical Engineering Award Committee, a member of Steering Committee of the IEEE Transactions on Biomedical Circuits and Systems. He was the Editor-in-Chief of the IEEE Transactions on Circuits and Systems II for two terms from 2010 to 2013. He served many positions in the IEEE CAS Society including Vice President for Publications, Vice President for Asia Pacific Region, Chair of the Biomedical Circuits and Systems Technical Committee, Chair of DSP Technical Committee, Distinguished Lecturer, etc. He is the founder of several conferences including BioCAS, ICGCS, and PrimeAsia.

Speech Title: Energy Efficient System Architecture for Devices in Artificial Intelligence of Things
Abstract: Internet-of-Things (IoT) is the inter-networking of physical devices, vehicles, buildings, and objects with embedded sensors. It is estimated that by 2020 there will be more than 34 billion IoT devices connected to the Internet. Nearly $6 trillion will be spent on IoT solutions over the next five years. Artificial Intelligence (AI), on the other hand, is intelligence demonstrated by machines that work and react like humans. Some examples of AI powered applications are voice-powered personal assistants like Siri and Cortana, machine translation, email spam filter, etc. The combination of AI and IoT gives birth of Artificial Intelligence of Things (AIoT). AIoT devices differ from IoT devices that not only they sense, store, transmit data but also analyze and act on data, i.e. the AIoT device makes a decision or perform a task similar to what a person could do. Most of existing “smart” IoT devices, which are controllable from an APP, are not AIoT devices. The true AIoT devices should be able to perform a task on your behalf, such as autonomous vehicle – it drives for you. The enabling technology for the AIoT device is embedded AI. This talk will cover low power techniques for embedded AI in AIoT applications. The focus is on the energy efficient system architecture that utilizes the brain-inspired event-driven signal representation. The event-driven signal representation enables data compression at the input source, which greatly reduces the power for data transmission and processing. We will show by examples that the event-driven system significantly improves energy efficiency and is well suited for AIoT applications.

 

 


Meng-Fan Chang,

National Tsing Hua University, Taiwan
Professor, EE Dept., National Tsing Hua University (NTHU), Taiwan
Program Director, Microelectronics Program, Ministry of Science and Technology (MOST), Taiwan, 2018-2020
IEEE Distinguished Lecturer (DL), Circuits and System Society (CASS)

Bography: Dr. Chang is a full Professor in the Dept. of Electrical Engineering of National Tsing Hua University (NTHU), Taiwan. Dr. Change obtained considerable practical experience before joining NTHU in 2006, having spent more than 10 years working in industry.
Between 1997 and 2006, Dr. Chang worked in the development of SRAM/ROM/Flash macros/compilers at Mentor Graphics (New Jersey, US), TSMC (Taiwan), and the Intellectual Property Library Company (Taiwan). His research interests include circuit design for volatile and nonvolatile memory, 3D-Memory, nonvolatile and spintronics logics, circuit-device-interactions in non-CMOS devices, memristor circuits, computing-in-memory and neuromorphic circuits for deep learning and artificial intelligent (AI) chips.            

Since 2010, Dr. Chang has authored or co-authored more than 40+ top conference papers (including 14 ISSCC, 15 VLSI Symposia, 8 IEDM, and 5 DAC) as well as 40+ IEEE journal papers and 40+ US patents. He is an associate editor for IEEE TVLSI, and IEEE TCAD. He has been serving on technical program committees for ISSCC, IEDM (Executive committee, Chair of MT sub-committee), DAC, A-SSCC, IEEE CAS Society (Chair Elect of NG-TC), and numerous international conferences. He is a Distinguished Lecturer (DL) for IEEE Circuits and Systems Society (CASS) during 2017-2018. He is the recipient of several prestigious national-level awards in Taiwan, including the Outstanding Research Award of MOST-Taiwan, Outstanding Electrical Engineering Professor Award, Ta-You Wu Memorial Award, Academia Sinica Junior Research Investigators Award, Outstanding Chip Design Awards, and Golden Silicon Awards. He currently is the Program Director of the Microelectronics Program at the Ministry of Science and Technology (MOST) in Taiwan.

Speech Title: Next-Generation Energy-Efficient Computing for IoT and AI Chips: How to Overcome the Memory Wall
Abstract: Memory has proven a major bottleneck in the development of energy-efficient chips for IoT applications and artificial intelligence (AI). Recent memory devices not only serve as memory macros, but also enable the development of nonvolatile logics (nvLogics) and computing-in-memory (CIM) for IoT and AI chips. In this talk, we will review recent trend of IoT and AI chips. Then, we will examine some of the challenges, circuits-devices-interaction, and recent progress involved in the further development of SRAM, emerging memory (STT-MRAM, ReRAM and PCM), nvLogics and CIMs for IoT and AI chips.

 

Zhangming Zhu
Xidian University, China

Bography: Prof. Zhangming Zhu (1978-) is currently a full Professor with the School of Microelectronics in Xidian University, Xi'an, China. He received the Ph.D. degrees in Microelectronics from the Xidian University, China, in 2004. Since 2004, he has been a lecturer of Xidian University. He was promoted to associate professor and full professor in 2005 and 2009, respectively, both with exceptive admission.. In 2013, he was appointed as the Chief Professor (Director ) of the Key Innovative Research Team of Shaanxi Province, China. He was the recipient of the National Science Fund for Distinguished Young Scholar and Excellent Young Scholar (selected by the National Natural Science Foundation of China), the New Century Excellent Talent in University (selected by the Ministry of Education of China).

Zhu's research interests are broadly in the area of data converters and analog front end (AFE), IPD based TSV , RF-ICs. He has authored/coauthored over 100 papers in journal, including IEEE TCAS-I, IEEE TMTT, IEEE TIE, IEEE TPE, IEEE TCAS-II, IEEE TIM, IEEE MWCL, IEEE TVLSI, IEEE TED.

Speech Title: High Speed CMOS Analog-to-digital Converter Based Successive Approximation Register
Abstract: Successive Approximation Register (SAR) analog-to-digital converters (ADCs) benefit from their simple configuration and mostly dynamic operation exhibiting excellent power and area efficiency under technology down scaling. The SAR architecture demands a stringent noise requirement for the comparator while aiming for high resolution. The signal-to-noise ratio (SNR) is usually dominated by the comparator’s thermal noise. The mismatch spurs due to the timing, offset and gain limit both signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR).  In this talk, some key technique for high speed SAR-based ADCs will been discussed.

 

 


David Z. Pan,
The University of Texas at Austin, United States

Bography:
David Z. Pan (IEEE Fellow, SPIE Fellow) received his BS degree from Peking University and MS/PhD degrees from UCLA. He is currently Engineering Foundation Professor at the Department of Electrical and Computer Engineering, The University of Texas at Austin.  His research interests include cross-layer IC design for manufacturing, reliability, security, machine learning in EDA, hardware acceleration, design/CAD for analog/mixed signal designs and emerging technologies such as nanophotonics. He has published over 320 refereed journal/conference papers and 8 US patents. He has served in many journal editorial boards and conference committees, including various leadership roles. He has received many prestigious awards, including SRC Technical Excellence Award, 16 Best Paper Awards, DAC Top 10 Author Award in Fifth Decade, ASP-DAC Frequently Cited Author Award, Communications of ACM Research Highlights, ACM/SIGDA Outstanding New Faculty Award, NSF CAREER Award, IBM Faculty Award (4 times), UCLA Engineering Distinguished Young Alumnus Award, UT Austin RAISE Faculty Excellence Award,  and many international CAD contest awards, among others. His students have also won many awards, including the First Place of ACM Student Research Competition Grand Finals in 2018, ACM/SIGDA Student Research Competition Gold Medal (twice), ACM Outstanding PhD Dissertation in EDA (twice), EDAA Outstanding Dissertation Award, and so on.

Speech Title: AI and Intelligent IC Design/Manufacutring
Abstract:
Artificial intelligence (AI) studies the theory and development of computing systems able to learn, reason, act and adapt. Integrated circuit (ICs), powered by the semiconductor technology, enable all modern computing systems with amazing level of integration, e.g., a small chip (<1cm2) nowadays can integrate billions of transistors. As the semiconductor technology enters the era of extreme scaling (1x nm), IC design and manufacturing complexities are extremely high. Intelligent cross-layer design and manufacturing co-optimizations are in critical demand for better performance, power, yield, reliability, security, time-to-market, and so on. This talk will discuss the synergy between modern AI technologies (e.g., pattern recognition, machine learning, deep learning) with intelligent deep-nanoscale IC design and manufacturing. Several case studies will be presented on AI for IC, including advanced lithography modeling, hotspot detection, mask synthesis, physical design, and security. Meanwhile, customized ICs for AI can further improve the training and inference performance-energy efficiency by orders of magnitude. Thus, the co-evolution of AI algorithms and IC technologies shall be investigated jointly to enhance the research and development of each other.